CMOS-Based Single-Cycle in-Memory XOR/XNOR

CMOS-Based Single-Cycle in-Memory XOR/XNOR

Blog Article

Big data applications are on the rise, and so is the number of data centers.The ever-increasing massive data pool needs to be periodically backed up in a secure Gift Items » Bedding environment.Moreover, a massive amount of securely backed-up data is required for training binary convolutional neural networks for image classification.XOR and XNOR operations are essential for large-scale data copy verification, encryption, and classification algorithms.The disproportionate speed of existing compute and memory units makes the von Neumann architecture inefficient to perform these Boolean operations.

Compute-in-memory (CiM) has proved to be an optimum approach for such bulk computations.The Top Gasket Sensor existing CiM-based XOR/XNOR techniques either require multiple cycles for computing or add to the complexity of the fabrication process.Here, we propose a CMOS-based hardware topology for single-cycle in-memory XOR/XNOR operations.Our design provides at least $2 imes $ improvement in the latency compared with other existing CMOS-compatible solutions.We verify the proposed system through circuit/system-level simulations and evaluate its robustness using a 5000-point Monte Carlo variation analysis.

This all-CMOS design paves the way for practical implementation of CiM XOR/XNOR at scaled technology nodes.